The demand for more and more complicated integrated circuits that may be monolithically formed on a single chip is driven by a desire for more compact electronic devices, as well as the potential for simplified post-fabrication assembly and packaging of these devices. Simplifying the assembly and packaging of electronic devices may improve durability and quality, as well as potentially decrease the cost of manufacture for the completed devices.
One difficulty that designers of such systems on a chip often face is ensuring proper electrical isolation between different circuits within these monolithic chips. In multi-chip designs, electrical isolation can be achieved by placing circuits that are likely to experience undesirable levels of crosstalk on separate electrically isolated substrates; however, in system on a chip designs, chip designers have no such luxury.
FIG. 1 illustrates this potential issue for a monolithically integrated system on a chip using single substrate 100. Circuits 102 and 104 represent two circuits that form part of the total system, but which desirably are electrically isolated from one another. For example, circuit 102 may be a radio frequency (RF) circuit and circuit 104 may be a digital baseband circuit. If impedance 106 though substrate 100 between circuit 102 and circuit 104 has a sufficiently high value, for both baseband and RF signals in this example, then these two monolithic circuits may operate without significant crosstalk; however, if impedance 106 has a low value, then undesirable levels of crosstalk are likely to occur during operation.
Reducing the doping of substrate 100 and/or increasing the separation distance between circuits 102 and 104 may increase the value of impedance 106; however, these relatively simple approaches often prove to be undesirable in ever shrinking circuit designs.
T. Blalack et al. describe a number of alternative approaches in ON-CHIP RF ISOLATION TECHNIQUES (IEEE Proceedings of Bipolar/BiCMOS Circuits and Technology Meeting 2002). These alternative methods include separating circuits with trenches, guard rings, shielding, capacitive decoupling and package inductance. In the first of these approaches, the trenches are cut through a low impedance buried layer so that the chip is held together by a significantly higher impedance layer that is not cut by the trenches. The low impedance buried layer is connected to a low impedance AC ground to act as a shield between the circuits. The guard ring and shielding approaches require forming a patterned layer of conductor(s) to reduce crosstalk between the circuits.
The present invention uses a new approach to isolate multiple circuits that are monolithically formed on a single substrate.